
2011 Microchip Technology Inc.
DS39932D-page 25
PIC18F46J11 FAMILY
PORTB (continued)
RB4/PMA1/KBI0/RP7
RB4
PMA1
KBI0
RP7
14
I/O
O
I
I/O
DIG
TTL
DIG
Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 7
RB5/PMA0/KBI1/RP8
RB5
PMA0
KBI1
RP8
15
I/O
O
I
I/O
DIG
TTL
DIG
Digital I/O.
Parallel Master Port address.
Interrupt-on-change pin.
Remappable peripheral pin 8.
RB6/KBI2/PGC/RP9
RB6
KBI2
PGC
RP9
16
I/O
I
I/O
DIG
TTL
ST
DIG
Digital I/O.
Interrupt-on-change pin.
ICSP clock input.
Remappable peripheral pin 9.
RB7/KBI3/PGD/RP10
RB7
KBI3
PGD
RP10
17
I/O
I
I/O
DIG
TTL
ST
DIG
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
Remappable peripheral pin 10.
TABLE 1-4:
PIC18F4XJ11 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
44-
QFN
44-
TQFP
Legend:
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
DIG = Digital output
Note 1:
RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.